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| DATA SHEET PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 4-BIT SINGLE-CHIP MICROCOMPUTER MOS INTEGRATED CIRCUIT The PD75068 is a member of the 75X series of 4-bit single-chip microcomputers. The minimum instruction execution time of the PD75068's CPU is 0.95 s. In addition to this high-speed capability, the chip contains an A /D converter and furnishes high-performance functions such as the serial bus interface (SBI) function compliant with the NEC standard format, providing powerful features and high cost performance. The PD75068(A) is a high-reliability version of the PD75068. NEC also provides PROM versions suitable for small-scale production or evaluation samples in system development. The PD75P068 is the PROM version for the PD75064, 75066, 75068, and the PD75P068(A) is that for the PD75064(A), 75066(A), 75068(A). The detailed function descriptions are described in the document below. Please make sure to read this document before starting design. PD75068 User's Manual: IEU-1366 FEATURES * Variable instruction execution time advantageous to high-speed operation and power-saving: * * * 0.95 s, 1.91 s, or 15.3 s (at 4.19 MHz with the main system clock selected) 122 s (at 32.768 kHz with the subsystem clock selected) Capable of low-voltage operation: VDD = 2.7 to 6.0 V * A /D converter (8-bit resolution, successive approximation): 8 channels * * * * * Timer function: 3 channels On-chip NEC standard serial bus interface (SBI) Very low-power watch operation enabled (5 A TYP. at 3 V) Pull-up resistor option allowed for 27 I/O lines The PD75P068 and 75P068(A) (PROM versions) available: Capable of low-voltage operation (VDD = 2.7 to 6.0 V) APPLICATIONS * * PD75064, 75066, 75068 Home electronic appliances, air conditioners, cameras, and electronic measuring instruments PD75064(A), 75066(A), 75068(A) Automotive electronics 5 The information in this document is subject to change without notice. Document No. IC-3140B ( O.D. No. IC-8629B) Date Published December 1994 P Printed in Japan The mark 5 shows revised points. NEC CORPORATION 1993 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) The PD75064, 75066, 75068 and PD75064(A), 75066(A), 75068(A) differ only in their quality grade. Unless otherwise specified, this data sheet describes the PD75068 as the representative product. For products with the suffix (A) attached, please make the following substitutions when reading: PD75064 --> PD75064(A) PD75066 --> PD75066(A) PD75068 --> PD75068(A) ORDERING INFORMATION Part number Package 42-pin 44-pin 42-pin 44-pin 42-pin 44-pin 42-pin 44-pin 42-pin 44-pin 42-pin 44-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic shrink DIP (600 mil) QFP (10x10 mm) shrink DIP (600 mil) QFP (10x10 mm) shrink DIP (600 mil) QFP (10x10 mm) shrink DIP (600 mil) QFP (10x10 mm) shrink DIP (600 mil) QFP (10x10 mm) shrink DIP (600 mil) QFP (10x10 mm) Quality Grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special 5 5 5 5 5 5 PD75064CU-xxx PD75064GB-xxx-3B4 PD75066CU-xxx PD75066GB-xxx-3B4 PD75068CU-xxx PD75068GB-xxx-3B4 PD75064CU(A)-xxx PD75064GB(A)-xxx-3B4 PD75066CU(A)-xxx PD75066GB(A)-xxx-3B4 PD75068CU(A)-xxx PD75068GB(A)-xxx-3B4 Remark xxx : ROM code suffix Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 5 DIFFERENCE BETWEEN PD7506x SUBSERIES AND PD7506x(A) SUBSERIES Part number PD75064 PD75066 PD75064(A) PD75066(A) PD75068(A) Special Parameter Quality grade PD75068 Standard 2 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) FUNCTION OVERVIEW Item Instruction execution time Function * Main system clock : 0.95 s, 1.91 s, 15.3 s (at 4.19 MHz) * Subsystem clock : 122 s (at 32.768 kHz) * PD75064 : 4096 x 8 bits * PD75066 : 6016 x 8 bits * PD75068 : 8064 x 8 bits 512 x 4 bits Internal memory ROM RAM General register * When operating in 4 bits: * When operating in 8 bits: 32 12 CMOS input 8 4 Of these, seven with software-specifiable on-chip pull-up resistors I/O port 12 CMOS I/O Software-specifiable on-chip pull-up resistors Four pins can directly drive LEDs. 8 N-ch open-drain I/O Breakdown voltage: 10 V Mask-option-specifiable on-chip pull-up resistors Can directly drive LEDs. Timer 3 chs. * Timer/event counter * Basic interval timer : Applicable to watchdog timer * Watch timer : Capable of buzzer output Serial interface * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode 16 bits , fx/23, fx/24, fx/2 6 (Main system clock: at 4.19 MHz operation) Bit sequencial buffer Clock output function A/D converter * 8-bit resolution x 8 channels * Low-power operation possible : VDD = 2.7 to 6.0 V External : 3 , Internal : 3 External : 1, Internal : 1 Vectored interrupt Test input System clock oscillator * Ceramic/crystal oscillator for main system clock * Crystal oscillator for subsystem clock STOP / HALT mode -40 to +85 C Standby function Operating ambient temperature Operating supply voltage Package 2.7 to 6.0 V * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm) 3 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ****************************************************************************************** 2. BLOCK DIAGRAM ************************************************************************************************************************ 3. PIN FUNCTIONS ************************************************************************************************************************** 3.1 3.2 3.3 3.4 3.5 Port Pins *********************************************************************************************************************************************** Non-Port Pins *************************************************************************************************************************************** Pin Input/Output Circuits******************************************************************************************************************* Mask Option Selection ************************************************************************************************************************ Handling Unused Pins ************************************************************************************************************************* 5 7 8 8 9 10 12 13 4. MEMORY CONFIGURATION ***************************************************************************************************** 14 5. PERIPHERAL HARDWARE FUNCTIONS *********************************************************************************** 18 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Ports ****************************************************************************************************************************************************** Clock Generator *********************************************************************************************************************************** Clock Output Circuit **************************************************************************************************************************** Basic Interval Timer ***************************************************************************************************************************** Watch Timer ***************************************************************************************************************************************** Timer/Event Counter *************************************************************************************************************************** Serial Interface ************************************************************************************************************************************* A/D Converter ************************************************************************************************************************************** Bit Sequential Buffer *************************************************************************************************************************** 18 19 20 21 22 23 24 25 26 6. INTERRUPT FUNCTIONS *********************************************************************************************************** 7. STANDBY FUNCTION **************************************************************************************************************** 8. RESET OPERATION ******************************************************************************************************************** 9. INSTRUCTION SET ******************************************************************************************************************** 10. ELECTRICAL SPECIFICATIONS ************************************************************************************************* 27 29 30 32 40 11. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) *********************************************************** 54 12. PACKAGE DRAWINGS *************************************************************************************************************** 60 13. RECOMMENDED SOLDERING CONDITIONS *************************************************************************** 62 APPENDIX A. APPENDIX B. DEVELOPMENT TOOLS **************************************************************************************** RELATED DOCUMENTS **************************************************************************************** 64 65 4 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 1. PIN CONFIGURATION (TOP VIEW) * 42-pin plastic shrink DIP XT1 XT2 RESET X1 X2 P33 P32 P31 P30 AVSS AN7/KR3/P63 AN6/KR2/P62 AN5/KR1/P61 AN4/KR0/P60 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVREF IC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40 P41 P42 P43 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ PD75064CU-xxx PD75066CU-xxx PD75068CU-xxx * 44-pin plastic QFP P110/AN0 P20/PTO0 P23/BUZ P22/PCL P13/TI0 AVREF P111/AN1 P21 VDD 44 43 42 41 40 39 38 37 36 35 34 INT2/P12 INT1/P11 INT0/P10 SB1/SI/P03 SB0/SO/P02 SCK /P01 INT4/P00 P53 P52 P51 P50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 P112/AN2 P113/AN3 P60/KR0/AN4 P61/KR1/AN5 P62/KR2/AN6 P63/KR3/AN7 AVSS P30 P31 P32 P33 PD75064GB-xxx-3B4 PD75066GB-xxx-3B4 PD75068GB-xxx-3B4 XT1 IC XT2 RESET X1 NC P43 P42 P41 IC : Internally Connected (This pin should be directly connected to VDD) P40 VSS X2 NC 5 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) PIN IDENTIFICATIONS P00 - 03 P10 - 13 P20 - 23 P30 - 33 P40 - 43 P50 - 53 P60 - 63 KR0 - 3 SCK SI SO SB0, 1 RESET TI0 PTO0 BUZ PCL INT2 X1, 2 XT1, 2 AN0 - 7 AVREF AVSS VDD VSS : : : : : : : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 11 Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Analog Input 0 - 7 Analog Reference Analog VSS Positive Power Supply Ground P110 - 113 : INT0, 1, 4 : 6 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 2. BLOCK DIAGRAM BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/ COUNTER #0 INTT0 PROGRAM Note COUNTER ALU BIT SEQ. BUFFER PORT 0 SP CY PORT 1 BANK 4 P00 - P03 4 P10 - P13 SI/SB1/P03 SO/SB0/P02 SCK/P01 SERIAL INTERFACE INTCSI PORT 2 4 P20 - P23 PORT 3 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0 - KR3 / P60 - P63 4 GENERAL REGISTER 4 P30 - P33 INTERRUPT CONTROL ROM PROGRAM MEMORY 4096 x 8 BITS ( PD75064) 6016 x 8 BITS ( PD75066) 8064 x 8 BITS ( PD75068) PORT 4 4 P40 - P43 DECODE AND CONTROL RAM DATA MEMORY 512 x 4 BITS PORT 5 4 P50 - P53 PORT 6 4 P60 - P63 BUZ/P23 WATCH TIMER INTW PORT 11 4 P110 - P113 AVREF AVSS AN0 - AN3 / P110 - P113 AN4 - AN7 / P60 - P63 8 A/D CONVERTER fX/2N CLOCK OUTPUT CONTROL CLOCK GENERATOR SUB MAIN CPU CLOCK CLOCK DIVIDER STAND BY CONTROL PCL/P22 XT1 XT2 X1 X2 VDD VSS RESET Note The PD75064 uses the program counter of a 12-bit configuration, the PD75066 and PD75068 use that of a 13-bit configuration. 7 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 3. 3.1 PIN FUNCTIONS Port Pins Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30Note 2 P31Note 2 P32Note 2 P33Note 2 P40 P43Note 2 I/O I/O I/O Input/ output Input I/O I/O I/O Input Shared with INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 - PCL BUZ - - - - - N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided for each bit (mask option). Breakdown voltage is 10 V in open-drain mode. High level (when pullup resistors are provided) or high impedance High level (when pullup resistors are provided) or high impedance x Input M Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. x Input E-B 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. x Input E-B With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. x Input Function 4-bit input port (PORT0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits. 8-bit I/O x When reset Input I/O circuit type Note 1 B F -A F -B M -C B -C P50 - P53Note 2 I/O - N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided for each bit (mask option). Breakdown voltage is 10 V in open-drain mode. M P60 P61 P62 P63 P110 P111 P112 P113 I/O KR0/AN4 KR1/AN5 KR2/AN6 KR3/AN7 Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. Y -D Input AN0 AN1 AN2 AN3 4-bit input port (PORT11). x Input Y-A Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. Can directly drive LEDs. 8 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 3.2 Non-Port Pins Pin name TI0 Input/ output Input Shared with P13 Function Input for receiving external event pulse signal for timer/event counter Timer/event counter output Clock output Output frequency selectable (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial bus I/O Serial data input Serial bus I/O Edge-detective vectored interrupt input (both rising and falling edges enabled) Edge-detective vectored interrupt input (detection edge selectable) Edge-detective testable input (rising edge detection) Note 2 Note 3 Note 3 When reset - I/O circuit typeNote 1 B -C PTO0 PCL BUZ I/O I/O I/O P20 P22 P23 Input Input Input E-B E-B E-B SCK SO/SB0 I/O I/O P01 P02 Input Input F -A F -B SI/SB1 I/O P03 Input M -C INT4 Input P00 - B INT0 INT1 INT2 Input P10 P11 - B -C Input P12 - B -C KR0 - KR3 I/O P60 - P63/ Parallel falling edge detection testable input AN4 - AN7 P110 - P113 For A /D converter only P60 - P63/ KR0 - KR3 - - - Reference voltage input GND potential Crystal/ceramic connection for main system clock generation. When external clock signal is used, the signal should be applied to X1, and its reverse phase signal to X2. Crystal connection for subsystem clock generation. When external clock signal is used, the signal should be applied to XT1, and its reverse phase signal to XT2. XT1 can be used as a 1-bit input (test). System reset input Internally connected. (Connect this pin directly to VDD) 8-bit analog input Input Y -D AN0 - AN3 AN4 - AN7 Input I/O Input Y-A Y -D AVREF AVSS X1, X2 Input - Input - - - Z Z - XT1, XT2 Input - - - RESET IC Input - - - - - B - VDD VSS - - - - Positive power supply GND potential - - - - Notes 1. The circle ( 3. Asynchronous ) indicates the Schmitt trigger input. 2. Clock synchronous 9 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 3.3 Pin Input/Output Circuits The input/output circuit of each PD75068 pin is shown below in a simplified manner. (1/3) Type A (For type E-B) Type D (For type E-B, F-A) VDD Data P-ch IN Output disable N-ch P-ch OUT VDD N-ch CMOS input buffer Type B Push-pull output which can be set to high impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable P-ch IN Data Type D Output disable IN/OUT Type A Schmitt trigger input with hysteresis Type B-C P.U.R.: Pull-Up Resistor VDD P.U.R. P.U.R. enable P-ch IN P.U.R.: Pull-Up Resistor 10 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) (2/3) Type F-A Type M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT Data Type D Output disable IN/OUT Data Output disable Type B VDD P.U.R. P.U.R. enable P-ch N-ch P.U.R.: Pull-Up Resistor Type F-B VDD P.U.R. P.U.R.: Pull-Up Resistor Type Y (For type Y-A , Y-D) VDD P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch AVSS VDD P-ch IN/OUT AVSS Reference voltage (from voltage tap of serial resistor string) Input enable P-ch IN VDD P-ch N-ch + Sampling C - P.U.R.: Pull-Up Resistor Type M VDD P.U.R. enable (Mask option) Type Y-A IN/OUT IN instruction Data Output disable N-ch (Can withstand +10 V) Type A Input buffer IN Type Y Middle-voltage input buffer (Can withstand +10 V) P.U.R.: Pull-Up Resistor 11 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) (3/3) Type Y-D VDD Type Z P.U.R. P.U.R. enable P-ch AVREF Data Type D Output disable IN/OUT Reference voltage Type B Type Y AVSS P.U.R.: Pull-Up Resistor 3.4 Mask Option Selection The following mask options are available for selection for each pin. Pin name P40 - P43, P50 - P53 XT1, XT2 Mask option 1 Pull-up resistor enabled (specifiable bit by bit) Feedback resistor enabled (if a subsystem clock is used) 2 Pull-up resistor disabled (specifiable bit by bit) Feedback resistor disabled (if a subsystem clock is not used) 1 2 12 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 3.5 Handling Unused Pins Table 3-1. Handling Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 P40-P43 P50-53 P60/KR0/AN4-P63/KR3/AN7 P110/AN0-P113/AN3 AVREF AVSS XT1 XT2 IC Recommended connection Connect to VSS. Connect to VSS or VDD. Connect to VSS. Input state: Connect to VSS or VDD. Output state: Open Connect to VSS or VDD. Connect to VSS. Connect to VSS or VDD. Open Directly connect to VDD. 13 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 4. MEMORY CONFIGURATION * Program memory (ROM) ..... 4096 x 8 bits (0000H to 0FFFH) : PD75064 ..... 6016 x 8 bits (0000H to 177FH) : PD75066 ..... 8064 x 8 bits (0000H to 1F7FH) : PD75068 * 0000H to 0001H : Vector table in which the program start address by reset is stored * 0002H to 000BH : Vector table in which the program start address by interrupt is stored * 0020H to 007FH : Table area to be referenced by GETI instruction * Data memory * Data area ..... 512 x 4 bits (000H to 1FFH) * Peripheral hardware area ..... 128 x 4 bits (F80H to FFFH) Figure 4-1. Program Memory Map (a) PD75064 Address 0000H 7 MBE 6 0 5 0 4 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) 0002H MBE 0 0 0 INTBT/INT4 start address INTBT/INT4 start address 0004H MBE 0 0 0 INT0 start address INT0 start address 0006H MBE 0 0 0 INT1 start address INT1 start address 0008H MBE 0 0 0 INTCSI start address INTCSI start address 000AH MBE 0 0 0 INTT0 start address INTT0 start address (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0 BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address 07FFH 0800H Branch destination address specified by GETI instruction, Subroutine entry address 0FFFH 14 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) (b) PD75066 Address 0000H 7 MBE 6 0 5 0 Internal reset start address Internal reset start address (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) 0 0002H MBE 0 0 INTBT/INT4 start address INTBT/INT4 start address 0004H MBE 0 0 INT0 start address INT0 start address 0006H MBE 0 0 INT1 start address INT1 start address CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0008H MBE 0 0 INTCSI start address INTCSI start address BR ! addr instruction brach address 000AH MBE 0 0 INTT0 start address INTT0 start address BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address 07FFH 0800H Branch destination address specified by GETI instruction, Subroutine entry address 0FFFH 1000H BRCB ! caddr instruction branch address 177FH 15 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) (c) PD75068 Address 0000H 7 MBE 6 0 5 0 Internal reset start address Internal reset start address (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) 0 0002H MBE 0 0 INTBT/INT4 start address INTBT/INT4 start address 0004H MBE 0 0 INT0 start address INT0 start address 0006H MBE 0 0 INT1 start address INT1 start address CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0008H MBE 0 0 INTCSI start address INTCSI start address BR ! addr instruction brach address 000AH MBE 0 0 INTT0 start address INTT0 start address BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address 07FFH 0800H Branch destination address specified by GETI instruction, Subroutine entry address 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH 16 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Figure 4-2. Data Memory Map Data memory General 000H register area 007H 008H Stack area 256 x 4 (8 x 4) Bank 0 Static RAM (512 x 4) 0FFH 100H 256 x 4 Bank 1 1FFH Not contained F80H Peripheral hardware area FFFH 128 x 4 Bank 15 17 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports The following three types of I/O port are provided: * CMOS input ports (PORT0, 1, 11) * CMOS input/output ports (PORT2, 3, 6) : 12 : 12 8 32 * N-ch open-drain input/output ports (PORT4, 5) : Total Table 5-1. Functions of Port Port (Symbol) PORT0 PORT1 PORT3Note PORT6 PORT2 PORT4Note PORT5Note Function 4-bit input Operation/features Can be read or tested regardless of the operation mode of the dual function pin. Can be specified for input/ output in bit units. Can be specified for input/ output in 4-bit units. Remarks Shared with the SO/SB0, SI/SB1, SCK, INT0-2, 4, and TI0 pins. 4-bit I/O Port 6 is shared with pins KR0 to KR3 and pins AN4 to AN7. Port 2 is shared with PTO0, PCL, and BUZ pins. Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. 4-bit I/O (N-ch open-drain, can withstand 10 V) Can be specified for input/ output in 4-bit units. Ports 4 and 5 can be paired to input/output data in 8-bit units. 4-bit port dedicated to input PORT11 4-bit input Port 11 is shared with pins AN0 to AN3. Note Can directly drive LEDs. 18 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.2 Clock Generator The clock generator operates according to the statuses of the processor clock control register (PCC) and the system clock control register (SCC). Two types of clock are provided: main system clock and subsystem clock, and the instruction execution time can be changed. * 0.95 s / 1.91 s / 15.3 s (operated with main system clock at 4.19 MHz) * 122 s (operated with subsystem clock at 32.768 kHz) Figure 5-1. Clock Generator Block Diagram * Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * A /D converter (successive approximation type) * INT0 noise eliminator * Clock output circuit XT1 Subsystem clock generator fXT Watch timer XT2 X1 X2 Main system clock generator fX 1/2 1/16 1/2 to 1/4096 Frequency divider WM.3 SCC SCC3 Oscillator disable signal Selector Frequency divider Selector 1/4 SCC0 Internal bus PCC PCC0 * CPU * INT0 noise eliminator * Clock output circuit PCC1 4 HALT Note HALT F/F PCC2 S STOP Note PCC3 R Q PCC2, PCC3 clear signal STOP F/F Q S Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor clock control register SCC: System clock control register One clock cycle (tCY) at is equal to one machine cycle of an instruction. For tCY, refer to AC Characteristics in 10. ELECTRICAL SPECIFICATIONS. 19 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.3 Clock Output Circuit The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to remote unit controller and peripheral LSIs. * Clock output (PCL): , 524 kHz, 262 kHz, 65.5 kHz (fX = at 4.19 MHz) Figure 5-2. Clock Output Circuit Configuration From the clock generator fX / 23 Selector fX / 2 fX / 2 4 Output buffer P22/PCL 6 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM Bit 2 of PMGB Port 2 input/ output mode specification bit P22 output latch 4 Internal bus Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable. 20 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.4 Basic Interval Timer The basic interval timer has these functions: * Interval timer operation which generates a reference timer interrupt * Watchdog timer application which detects a program runaway * Selection of wait time for releasing the standby mode and counting the wait time * Reading out the count value Figure 5-3. Basic Interval Timer Configuration From the clock generator fX/25 fX/2 fX/2 fX/2 7 Clear signal Clear signal MPX 9 Basic interval timer (8-bit frequency divider circuit) Set signal BT interrupt request flag 12 BT IRQBT Vectored interrupt request signal 3 Wait release signal for standby release BTM0 BTM 8 Internal bus BTM3 SET1 Note BTM2 BTM1 4 Note Instruction execution 21 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.5 Watch Timer The PD75068 has an on-chip 1-ch watch timer. The watch timer has the following functions: * Sets the test flag (IRQW) with a 0.5-sec interval. The standby mode can be released by IRQW. * The 0.5-second interval can be generated from either the main system clock or subsystem clock. * The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for program debugging, testing, etc. * Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. * The frequency divider circuit can be cleared so that a zero-second start of the watch can be made. Figure 5-4. Watch Timer Block Diagram fw 27 (256 Hz: 3.91 ms) From the clock generator fX 128 (32.768 kHz) fXT (32.768 kHz) fW (32.768 kHz) Selector Frequency divider (4 kHz)(2 kHz) fw 214 2 Hz 0.5 sec Clear signal Selector INTW IRQW set signal fw 23 fw 24 Selector Output buffer P23/BUZ WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 PORT2.3 P23 output latch Bit 2 of PMGB Port 2 input/ output mode 8 Bit test instruction Internal bus Remark ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz. 22 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.6 Timer/Event Counter The PD75068 has an on-chip 1-ch timer/event counter. The timer/event counter has the following functions: * Programmable interval timer operation * Outputs square-wave signal of a user-selectable frequency to the PTO0 pin * Event counter operation * Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation) * Supplies serial shift clock to the serial interface circuit * Count condition read-out function. Figure 5-5. Block Diagram of Timer / Event Counter Internal bus 8 SET1 Note TM0 8 8 TMOD0 Modulo register (8) TOE0 TO enable flag PORT2.0 P20 output latch signal Bit 2 of PGMB Port 2 input/ output mode TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 PORT1.3 8 Match To serial interface TOUT F/F Reset T0 INTT0 Output buffer P20/PTO0 Comparator (8) 8 Input buffer P13/ TI0 From the clock generator Count register (8) MPX CP Clear signal Timer operation start signal IRQT0 set signal (Refer to Fig. 5-1.) RESET IRQT0 clear signal Note Instruction execution 23 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.7 Serial Interface (1) Serial interface function The PD75068 contains a clock synchronous 8-bit serial interface, which has four modes. * Operation halt mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI (serial bus interface mode) Figure 5-6. Block Diagram of Serial Interface Internal bus 8/4 CSIM Bit test 8 8 8 Slave address register (SVA) (8) Match signal (8) RELT CMDT SO SET CLR latch D Q ACKE ACKT BSYE Bit manipulation SBIC Bit test Address comparator P03/SI/SB1 Selector Shift register (SIO) (8) P02/SO/SB0 Selector Busy/ acknowledge output circuit Bus release/ command/ acknowledge detection circuit P01/SCK RELD CMDD ACKD INTCSI Serial clock counter P01 output latch INTCSI control circuit IRQCSI set signal fx/23 fx/24 fx/26 TOUT F/F (from timer/ event counter) Serial clock control circuit Serial clock selector External SCK 24 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.8 A/D Converter The PD75068 contains an 8-bit analog/digital (A / D) converter that has eight analog input channels (AN0 - AN7). The A /D converter employs the successive-approximation method. Figure 5-7. Block Diagram of A/D Converter Internal bus 8 0 ADM6 ADM5 ADM4 SOC EOC ADM1 0 ADM 8 AN0/P110 AN1/P111 AN2/P112 Control circuit Sample and hold circuit + AN3/P113 AN4/KR0/P60 AN5/KR1/P61 AN6/KR2/P62 Multiplexer - Comparator SA register (8) 8 AN7/KR3/P63 Tap decoder AVREF R/2 R R Series resistor string R R/2 AVSS 25 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5.9 Bit Sequential Buffer: 16 Bits The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Figure 5-8. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 BSB3 0 3 FC2H 2 1 BSB2 0 3 FC1H 2 1 BSB1 0 3 FC0H 2 1 BSB0 0 L register L=F L=C L=B L=8 L=7 L=4 L=3 DECS L L=0 INCS L Remark For "pmem.@L" addressing, the specification bit is shifted according to the L register. 26 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 6. INTERRUPT FUNCTIONS The PD75068 has six different interrupt sources. In addition, multiple interrupts with priority control are possible. Two types of test sources are provided. Of these test sources, INT2 has two types of edge detection testable inputs. Table 6-1. Interruption Source Types Interruption Source (Reference time interval signal from basic interval timer) (Detection of both rising edge and falling edge is valid.) (Selection of rising edge detection or falling edge detection) (Serial data transmission completion signal) (Coincidence signal of programmable timer/counter count register and modulo register) (Detection of rising edge of input to INT2 pin or detection of falling edge of any input to KR0 to KR3) (Signal from watch timer) IN/OUT Interruption OrderNote1 Vectored Interrupt Request Signal (Vector table address) INTBT INT4 INT0 INT1 INTCSI IN 1 OUT OUT OUT IN 2 3 4 VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ1 (0002H) INTT0 IN 5 VRQ5 (000AH) INT2Note2 INTWNote2 OUT Test input signal (Set IRQ and IRQW) IN Notes 1. The interruption order shows the priority order of the pins when several interruption requests occur at the same time. 2. Test source. Like the interruption source, it is influenced by the interruption enable flag. However, vectored interrupt will not occur. The interrupt control circuit of the PD75068 has the following functions: * Hardware controlled vectored interrupt function which can control whether or not to acknowledge an interrupt based on the interrupt flag (IExxx) and interrupt master enable flag (IME) * The interrupt start address can be set arbitrarily. * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by software) * Standby mode release (interrupts to be released can be selected by the interrupt enable flag) 27 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Figure 6-1. Block Diagram of Interrupt Control Circuit Internal bus 1 IM1 3 IM0 Interrupt enable flag (IExxx) IME IST0 INT BT INT4 /P00 INT0 /P10 INT1 /P11 Both-edge detection circuit Edge detection circuit Edge detection circuit Decoder IRQBT VRQn IRQ4 Note IRQ0 IRQ1 Priority control circuit INTCSI IRQCSI Vector table address generator INTT0 IRQT0 INTW INT2 /P12 AN4/KR0/P60 Falling edge detection circuit Rising edge detection circuit IRQW Selector IRQ2 Standby release signal AN7/KR3/P63 IM2 Note Noise eliminator 28 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 7. STANDBY FUNCTION The PD75068 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while waiting for program execution. Table 7-1. Standby Mode Statuses STOP mode Instruction for setting System clock for setting STOP instruction Can be set only when operating on the main system clock. Only the main system clock stops its operation. Does not operate. HALT mode HALT instruction Can be set either with the main system clock or the subsystem clock. Only the CPU clock stops its operation (oscillation continues). Can operate only at main system clock oscillation (IRQBT is set at reference time intervals.). Can operate only when external SCK input is selected as the serial clock or at main system clock oscillation. Can operate only when TI0 pin input is specified as the count clock or at main system clock oscillation. Can operate. Can operate.Note Operation status Clock oscillator Basic interval timer Serial interface Can operate only when the external SCK input is selected for the serial clock. Timer/event counter Can operate only when the TI0 pin input is selected for the count clock. Watch timer Can operate when fXT is selected as the count clock. Does not operate. INT1, INT2, and INT4 can operate. Only INT0 cannot operate. Does not operate. An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the RESET signal input A/D converter External interrupt CPU Release signal An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the RESET signal input Note A/D converter's operation in HALT mode is possible only when the main system clock operates. 29 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 8. RESET OPERATION When the RESET signal is input, the PD75068 is reset and all hardware is initialized as indicated in Table 8-1. Figure 8-1 shows the reset operation timing. Figure 8-1. Reset Operation by RESET Input Wait (Approx. 31.3 ms/4.19 MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Table 8-1. Status of All Hardware after Reset (1/2) Hardware Program counter (PC) RESET input in standby mode RESET input during operation Same operation as that in standby state PD75064 Contents of lower 4 bits of address 0000H in program memory are set to PC11 - 8, and that of 0001H are set to PC7 - 0. Contents of lower 5 bits of address 0000H in program memory are set to PC12 - 8, and that of 0001H are set to PC7 - 0. Retained 0 0 The contents of bit 7 of address 0000H of the program memory is set to MBE. Undefined RetainedNote Retained PD75066 PD75068 Same operation as that in standby state PSW Carry flag (CY) Skip flag (SK0-2) Interrupt status flag (IST0) Bank enable flag (MBE) Undefined 0 0 Same operation as that in standby state Undefined Undefined Undefined Stack pointer (SP) Data memory (RAM) General purpose register (X, A, H, L, D, E, B, C) Bank selection register (MBS) Basic interval timer Timer/event counter Counter (BT) Mode register (BTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Watch timer Mode register (WM) 0 Undefined 0 0 FFH 0 0, 0 0 0 Undefined 0 0 FFH 0 0, 0 0 Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is input. 30 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Table 8-1. Status of All Hardware after Reset (2/2) Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, Clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Interrupt function Interrupt request flag ( IRQxxx ) IRQ1, IRQ2, and IRQ4 Other than above RESET input in standby mode Retained 0 0 Retained 0 RESET input during operation Undefined 0 0 Undefined 0 0 0 0 0 Undefined Undefined 0 0 0 0 0 0 Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0, 1, 2, mode register (IM0, IM1, IM2) Digital port Output buffer Output latch Input/output mode register (PMGA, PMGB) Pull-up resistor specification register (POGA) A/D converter Mode register (ADM) SA register (SA) Bit sequential buffer (BSB0-BSB3) 0, 0, 0 0, 0, 0 Off Clear (0) 0 Off Clear (0) 0 0 0 04H Undefined Retained 04H Undefined Undefined 31 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 9. INSTRUCTION SET (1) Operand identifier and its descriptive method The operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions. Details should be followed by "RA75X Assembler Package User's Manual, Language." For descriptions in which alternatives exist, one element should be selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as they are. For immediate data, the appropriate numerical values or labels should be described. Identifier reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 memNote bit fmem pmem addr X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H - FBFH, FF0H - FFFH immediate data or label FC0H - FFFH immediate data or label Description PD75064 PD75066 PD75068 0000H - 0FFFH immediate data or label 0000H - 177FH immediate data or label 0000H - 1F7FH immediate data or label caddr faddr taddr PORTn IExxx MBn 12-bit immediate data or label 11-bit immediate data or label 20H - 7FH immediate data (however, bit 0 = 0) or label PORT0 - PORT6, PORT11 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15 Note Only even address can be specified for mem when processing 8-bit data. (2) Symbol definitions in operation description A B C D E H L X XA BC DE : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Pair register (XA); 8-bit accumulator : Pair register (BC) : Pair register (DE) 32 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) HL PC SP CY PSW MBE IME IExxx MBS PCC . (xx) xxH : Pair register (HL) : Program counter : Stack pointer : Carry flag; Bit accumulator : Program status word : Memory bank enable flag : Interrupt master enable flag : Interrupt enable flag : Memory bank selection register : Processor clock control register : Address bit delimiter : Contents addressed by xx : Hexadecimal data PORTn : Port n (n = 0 to 6, 11) (3) Symbols used for the addressing area column *1 *2 *3 MB = MBE * MBS (MBS = 0, 1, 15) MB = 0 MBE = 0: MB = 0 (00H - 7FH) MB = 15 (80H - FFH) MBE = 1: MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H - FBFH, FF0H - FFFH MB = 15, pmem = FC0H - FFFH PD75064 PD75066 PD75068 Data memory addressing *4 *5 *6 addr = 0000H - 0FFFH addr = 0000H - 177FH addr = 0000H - 1F7FH *7 *8 addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 PD75064 PD75066 PD75068 caddr = 0000H - 0FFFH caddr = 0000H - 0FFFH (PC 12 = 0) or = 1000H - 177FH (PC12 = 1) caddr = 0000H - 0FFFH (PC 12 = 0) or = 1000H - 1F7FH (PC12 = 1) Program memory addressing *9 *10 faddr = 0000H - 07FFH taddr = 0020H - 007FH Remarks 1. MB indicates the memory bank that can be accessed. 2. For *2, MB = 0 regardless of MBE and MBS settings. 3. For *4 and *5, MB = 15 regardless of MBE and MBS. 4. For *6 to *10, each addressable area is indicated. 33 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) (4) Description of machine cycle column S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes as follows: * When no skip is performed ************************************************************************************************************ S = 0 * When a 1-byte or 2-byte instruction is skipped ****************************************************************************S = 1 * When a 3-byte instruction (BR !addr Note Note , CALL !addr instruction) is skipped *********************** S = 2 BR !addr instruction is not provided in the PD75064. Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equivalent to one CPU clock cycle. Therefore, the length of the machine cycle can be selected from three different lengths by the PCC setting. 5 (5) Representative products listed in operation column The products listed in the operation column (PD75064, 75066, 75068) stand for the products listed below. PD75064 PD75066 PD75068 PD75064, PD75064(A) PD75066, PD75066(A) PD75068, PD75068(A) 34 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) MaBytes chine cycle 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp * PD75064 XA (PC11-8 + DE)ROM * PD75066, 75068 XA (PC12-8 + DE)ROM XA, @PCXA 1 3 * PD75064 XA (PC11-8 + XA)ROM * PD75066, 75068 XA (PC12-8 + XA)ROM Arithmetic ADDS A, #n4 A, @HL ADDC SUBS SUBC A, @HL A, @HL A, @HL 1 1 1 1 1 1+S 1+S 1 1+S 1 A A + n4 A A + (HL) A, CY A + (HL) + CY A A - (HL) A, CY A - (HL) - CY *1 *1 *1 *1 borrow carry carry *1 *2 *1 *3 *3 *1 *2 *1 *1 *1 *3 *3 *3 *3 String A String B Group Mnemonic MOV Operand Operation Addressing area Skip condition String A Transfer A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp reg1, A rp1, XA XCH A, @HL A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp Table reference MOVT XA, @PCDE 35 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) MaBytes chine cycle 2 1 2 1 2 1 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1 2 1 1 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S AA Address- Skip ing area condition Group Mnemonic AND Operand Operation Arithmetic A, #n4 A, @HL OR A, #n4 A, @HL XOR A, #n4 A, @HL n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL) CY A0 , A A reg reg + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit(L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear A3 CY, An-1 An *1 *1 *1 Accumulator manipulation RORC NOT INCS A A reg @HL mem Increment/ decrement reg = 0 *1 *3 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 *1 (HL) = n4 A = (HL) A = reg DECS Comparison SKE reg reg, #n4 @HL, #n4 A, @HL A, reg Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem. @L @H+mem.bit CY = 1 Memory bit manipulation SET1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 CLR1 mem.bit fmem.bit pmem. @L @H+mem.bit SKT mem.bit fmem.bit pmem. @L @H+mem.bit SKF mem.bit fmem.bit pmem. @L @H+mem.bit (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 SKTCLR fmem.bit pmem. @L @H+mem.bit (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 36 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) MaBytes chine cycle 2 2 2 2 2 2 2 2 2 - 2 2 2 2 2 2 2 2 2 - CY CY Group Mnemonic AND1 Operand Operation Addressing area *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 Skip condition Memory bit manipulation CY, fmem.bit CY, pmem. @L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem. @L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit (fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit) Branch BR addr * PD75064 PC11-0 addr (Appropriate instructions are selected from BRCB !caddr, and BR $addr by the assembler.) * PD75066, 75068 PC12-0 addr (Appropriate instructions are selected from BR !addr, BRCB !caddr, and BR $addr by the assembler.) !addr Note 3 3 * PD75066, 75068 PC12-0 addr * PD75064 PC11-0 addr * PD75066, 75068 PC12-0 addr *6 $addr 1 2 *7 BRCB !caddr 2 2 * PD75064 PC11-0 caddr11-0 * PD75066, 75068 PC12-0 PC12 + caddr11-0 *8 Subroutine stack control CALL !addr 3 3 * PD75064 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, 0, 0, 0 PC11-0 addr, SP SP - 4 * PD75066, 75068 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 addr, SP SP - 4 *6 Note BR !addr instruction is not provided in the PD75064. 37 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) MaBytes chine cycle 2 2 Group Mnemonic CALLF Operand Operation * PD75064 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP-3) MBE, 0, 0, 0 PC11-0 00, faddr, SP SP - 4 * PD75066, 75068 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 00, faddr, SP SP - 4 Addressing area *9 Skip condition Subroutine stack control !faddr RET 1 3 * PD75064 MBE, 0, 0, 0 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 * PD75066, 75068 MBE, 0, 0, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 RETS 1 3+S * PD75064 MBE, 0, 0, 0 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4, then skip unconditionally * PD75066, 75068 MBE, 0, 0, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4, then skip unconditionally Unconditional RETI 1 3 * PD75064 MBE, 0, 0, 0 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 * PD75066, 75068 MBE, 0, 0, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 PUSH rp BS 1 2 1 2 1 2 1 2 (SP - 1)(SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) 0, SP SP - 2 rp (SP + 1)(SP), SP SP + 2 MBS (SP + 1), SP SP + 2 POP rp BS 38 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) MaBytes chine cycle 2 IExxx DI IExxx Input/ output IN A, PORTn XA, PORTn OUT PORTn, A PORTn, XA CPU control HALT STOP NOP Special SEL GETI MBn taddr 2 2 2 2 2 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 1 2 3 IME 1 IExxx 1 IME 0 IExxx 0 A PORTn (n = 0 - 6, 11) (n = 4, 6) (n = 2 - 6) Group Mnemonic EI Operand Operation Addressing area Skip condition Interrupt control XA PORTn+1,PORTn PORTn A PORTn+1, PORTn XA (n = 4, 6) Set HALT Mode Set STOP Mode No Operation MBS n (n = 0, 1, 15) * PD75064 * For the TBR instruction PC11-0 (taddr)3-0 + (taddr + 1) *10 (PCC.2 1) (PCC.3 1) ---------------------------------------------* For the TCALL instruction (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, 0, 0, 0 PC11-0 (taddr)3-0 + (taddr + 1) SP SP - 4 ----------------- ---------------------------------------------* For other than the TBR and TCALL instruction (taddr) (taddr + 1) is executed. ----------------Depends on the reference instruction. ---------------------------------------------* For the TCALL instruction (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, 0, 0, PC12 PC12-0 (taddr)4-0 + (taddr + 1) SP SP - 4 For other than the TBR and TCALL instruction (taddr) (taddr + 1) is executed. * PD75066, 75068 * For the TBR instruction PC12-0 (taddr)4-0 + (taddr + 1) ----------------- ---------------------------------------------* ----------------Depends on the reference instruction. Caution When executing the IN/OUT instruction, MBE must be set to 0, or MBE and MBS must be set to 1 and 15, respectively. 39 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (Ta = 25 C) Parameter Power supply voltage Symbol VDD VI1 Input voltage VI2 Ports 4 and 5 N-ch open-drain Output voltage High level output current VO Per pin IOH All output pins Low level output current Peak value One pin of ports 0, 3, 4, and 5 rms value Peak value IOLNote One pin of ports 2 and 6 rms value Peak value Total of ports 0, 3, 4 and 5 rms value Peak value Total of ports 2 and 6 rms value Operating ambient temperature Storage temperature Topt 20 -40 to +85 mA C C 120 30 mA mA 5 160 mA mA 15 20 mA mA -30 30 mA mA -0.3 to +11 -0.3 to VDD+0.3 -10 V V mA Except ports 4 and 5 On-chip pull-up resistor Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 Unit V V V Tstg -65 to +150 Note Rms value is calculated using the following expression: [rms value] = [peak value] x duty ratio Caution If any of the items exceeds the absolute maximum ratings, even momentarily, this may damage product quality. The absolute maximum ratings are values that may physically damage products. Be sure to use the products within the ratings. 40 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Main System Clock Oscillator Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Resonator Recommended Constant Parameter Conditions VDD = Oscillation voltage range MIN. TYP. MAX. Unit VSS X1 X2 Oscillation frequency (fx)Note1 1.0 5.0 Note3 MHz Ceramic resonator C1 C2 Oscillation stabilization timeNote2 Oscillation frequency (fx)Note1 VDD = 4.5 to 6.0 V 4 ms 1.0 4.19 5.0 Note3 MHz VSS X1 X2 Crystal resonator 10 ms C1 C2 Oscillation stabilization timeNote2 30 ms X1 X2 X1 input frequency (fx)Note1 1.0 5.0 Note3 MHz External clock PD74HCU04 X1 input high-/low-level width (tXH, tXL) 100 500 ns Notes 1. The oscillation frequency indicates characteristics of the oscillator only. For the instruction execution time, refer to the AC characteristics. 2. The oscillation stabilization time is the required time for oscillation to stabilize after the voltage level of VDD reaches the MIN. value of the oscillation voltage range or releasing the STOP mode. 3. When the oscillation frequency is "4.19 MHz < fX 5.0 MHz", selection of "PCC = 0011" with 1 machine cycle of less than 0.95 s for instruction execution time is not possible. Caution If the main system clock oscillator is used, the wiring in the area indicated with broken lines in the recommended constant illustration should be routed observing the points described below to avoid influence of wiring capacitance, etc. * Route as short as possible. * Do not cross the wires. * Route the wires away from lines where changing high current flows. * Make the connecting point of the capacitors in the oscillation circuit to have always the same potential as VSS. Do not route the connecting point to another ground pattern on the board where high current flows. * Do not use the oscillator as a signal source of other circuits. 41 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Subsystem Clock Oscillator Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Resonator Recommended Constant Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (fXT)Note1 VSS XT1 XT2 R 32 32.768 50 kHz Crystal resonator C3 VDD = 4.5 to 6.0 V C4 1.0 2 s Oscillation stabilization timeNote2 10 s XT1 input frequency (fXT)Note1 XT1 XT2 32 100 kHz External clock XT1 input high-/ low-level width (tXTH,tXTL) 5 15 s Notes 1. The oscillation frequency indicates characteristics of the oscillator only. For the instruction execution time, refer to the AC characteristics. 2. The oscillation stabilization time is the required time for oscillation to stabilize after the voltage level of VDD reaches the MIN. value of the oscillation voltage range. Caution If the subsystem clock oscillator is used, the wiring in the area indicated with broken lines in the recommended constant illustration should be routed observing the points described below to avoid influence of wiring capacitance, etc. * * * * Route as short as possible. Do not cross the wires. Route the wires away from lines where changing high current flows. Make the connecting point of the capacitors in the oscillation circuit to have always the same potential as VSS. Do not route the connecting point to another ground pattern on the board where high current flows. * Do not use the oscillator as a signal source of other circuits. Especially when using the subsystem clock, be sure to design wiring so as to minimize noise. The subsystem clock oscillator uses a low-amplification circuit to minimize power dissipation. As a result, malfunctions due to noise are more liable to occur than with the main system clock oscillator. 42 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Recommended Oscillator Constant Main system clock: Ceramic (Ta = -40 to +85C) Frequency (MHz) Recommended circuit constant C1 (pF) 47 C2 (pF) 47 Oscillation voltage range MIN. (V) 2.5 MAX. (V) Manufacturer Part number Remarks KBR-2.0 MS PBRC 2.00A KYOCERA KBR-4.19 MSA PBRC 4.19A KBR-4.19 MKS KBR-4.19 MWS CSB1000JNote CSA2.0MG040 MURATA Manufacturing CST2.0MGW093 CSAC2.0MGCME CSA4.19MGU 2.00 4.19 33 33 2.7 6.0 4.19 1.00 Internal 100 100 Internal 100 100 Internal 15 30 Internal 2.7 2.7 2.8 6.0 Chip product Rd = 5.6 k 2.00 Internal 15 30 4.19 CST4.19MGUW Internal Note When the Murata's CSB1000J ceramic resonator (1.00 MHz) is used, the limiting resistor (Rd = 5.6 k) is required (see figure below). When using other recommended resonators, the limiting resistor is not required. Example of Recommended Main System Clock Circuit (when using CSB1000J of Murata) X1 CSB1000J X2 Rd C1 C2 Main System Clock: XTAL Frequency (MHz) 2.00 DAISINKU HC-49/U 4.19 5.00 2.00 KINSEKI HC-49/U 4.19 22 22 3.2 3.1 6.0 (Ta = -20 to +70C) 8 8 Recommended circuit constant C1 (pF) C2 (pF) Oscillation voltage range MIN. (V) 2.8 2.7 6.0 (Ta = -40 to +85C) MAX. (V) Manufacturer Part number Remarks 43 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Parameter High-level input voltage Symbol VIH1 VIH2 Ports 2, 3, and 11 Ports 0,1,6, RESET On-chip pull-up resistor VIH3 Ports 4 and 5 N-ch open-drain VIH4 Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage VOH X1, X2, XT1, XT2 Ports 2 through 5 and 11 Ports 0, 1, 6, RESET X1, X2, XT1, XT2 VDD = 4.5 to 6.0 V , IOH = -1 mA IOH = -100 A VOL Ports 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA VDD = 4.5 to 6.0 V IOL = 15 mA 0.7 VDD VDD -0.5 0 0 0 VDD -1.0 VDD -0.5 0.7 2.0 10 VDD 0.3 VDD 0.2 VDD 0.4 V V V V V V V V Conditions MIN. 0.7 VDD 0.8 VDD 0.7 VDD TYP. MAX. VDD VDD VDD Unit V V V Low-level output voltage Port 3 0.3 2.0 V VDD = 4.5 to 6.0 V , IOL = 1.6 mA IOL = 400 A SB0, SB1 N-ch open-drain pull-up resistor 1 k Other than pins below VI = VDD ILIH2 ILIH3 Low-level input leakage current ILIL1 VI = 0 V ILIL2 High-level output leakage current ILOH1 ILOH2 Low-level output leakage current On-chip pull-up resistor ILOL VO = VDD VO = 10 V VO = 0 V VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % Ports 4 and 5 (N-ch open-drain) X1, X2, XT1, XT2 VI = 10 V X1, X2, XT1, XT2 Ports 4 and 5 (N-ch open-drain) Other than pins below 0.4 0.5 0.2 VDD V V V High-level input leakage current ILIH1 3 20 20 -3 -20 3 20 -3 A A A A A A A A RU1 P01, 02, 03, Ports 1, 2, 3 and 6 VI = 0 V Ports 4 and 5 VO = VDD - 2.0 V 15 30 15 10 40 80 300 k k k k (Cont.) 40 70 60 RU2 44 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Parameter Supply current Note1 Symbol Conditions VDD = 5.0 V 10 % Note3 MIN. TYP. 2.0 0.2 400 120 10 5 MAX. 6.0 0.6 1200 400 30 15 Unit mA mA IDDI 4.19 MHz Note2 crystal oscillation C1 = C2 = 22 pF IDD2 mode IDD3 IDD4 32.768 kHz Note5 crystal oscillation VDD = 3.0 V 10 % HALT Note4 VDD = 5.0 V 10 % VDD = 3.0 V 10 % A A A A VDD = 3.0 V 10 % HALT mode VDD = 3.0 V 10 % IDD5 XT1 = 0 V STOP mode VDD = 5.0 V 10 % VDD = 3.0 V 10 % Ta = 25 C 0.5 0.1 0.1 20 10 5 A A A Notes 1. Current which flows in the on-chip pull-up resistor is not included. 2. Including oscillation of the subsystem clock. 3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. 4. When PCC is set to 0000 and the device is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 45 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Capacitance (Ta = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF AC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Parameter CPU clock cycle time Note1 ( minimum instruction execution time = 1 machine cycle ) TI0 input frequency Symbol Conditions Operating on main system clock tCY Operating on subsystem clock VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 122 TYP. MAX. 64 64 125 Unit s s s VDD = 4.5 to 6.0 V fTI 0 0 1 275 MHz kHz TI0 input high and low level width tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 1.8 s s s s s s Interrupt input high and low level width INT0 tINTH, tINTL INT1, INT2, INT4 KR0 to KR3 Note2 10 10 10 RESET low level width tRSL Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator, the system clock control register (SCC), and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fX is set by setting the interrupt mode register (IM0). tCY vs VDD (Operating on Main System Clock) 70 64 60 6 5 4 Operation guarantee range Cycle Time tCY [ s] 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 46 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Serial Transfer Operation 2-Wire and 3-Wire Serial I/O Modes (SCK ... Internal clock output) Parameter SCK cycle time tKCY1 3800 SCK high- and lowlevel width tKL1 tKH1 VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 150 ns ns ns ns Symbol VDD = 4.5 to 6.0 V Conditions MIN. 1600 TYP. MAX. Unit ns SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tSIK1 tKSI1 VDD = 4.5 to 6.0 V Note 400 0 0 250 1000 ns ns ns tKSO1 RL = 1 k, CL = 100 pF 2-Wire and 3-Wire Serial I/O Modes (SCK ... External clock input) Parameter SCK cycle time tKCY2 3200 SCK high- and lowlevel width tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns Symbol VDD = 4.5 to 6.0 V Conditions MIN. 800 TYP. MAX. Unit ns SI setup time (to SCK) SI hold time (from SCK ) SO output delay time from SCK tSIK2 tKSI2 VDD = 4.5 to 6.0 V Note 400 0 0 300 1000 ns ns ns tKSO2 RL = 1 k, CL = 100 pF Note RL and CL are load resistance and load capacitance of the SO output line, respectively. 47 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) SBI Mode (SCK ... Internal clock output (Master)) Parameter SCK cycle time tKCY3 3800 SCK high- and low-level width tKL3 tKH3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 150 ns ns ns ns Symbol VDD = 4.5 to 6.0 V Conditions MIN. 1600 TYP. MAX. Unit ns SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tSIK3 tKSI3 VDD = 4.5 to 6.0 V Note tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns ns tKSO3 RL = 1 k, CL = 100 pF tKSB tSBK tSBL tSBH SBI Mode (SCK ... External clock input (Slave)) Parameter SCK cycle time tKCY4 3200 SCK high- and low-level width tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns Symbol Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tSIK4 tKSI4 VDD = 4.5 to 6.0 V Note tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns ns tKSO4 RL = 1 k, CL = 100 pF tKSB tSBK tSBL tSBH Note RL and CL are load resistance and load capacitance, respectively, for the SB0 and SB1 output lines. 48 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) A/D Converter (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Resolution Absolute accuracy Note1 -10 Ta +85 C -40 Ta < -10 C Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.5 2.0 168/fx 44/fX 2.5 AVSS 1000 0.7 2.0 VDD AVREF Unit bit LSB LSB 2.5 V AVREF VDDNote2 Conversion timeNote3 Sampling time Reference input voltage Analog input voltage Analog input impedance AVREF current Note4 tCONV tSAMP AVREF VIAN RAN AIREF s s V V M mA Notes 1. Absolute accuracy excluding quantization error (1/2 LSB) 2. ADM1 should be set according to the A/D converter reference voltage (AVREF) as follows: When the AVREF is between 0.6VDD and 0.65VDD, either 1 or 0 can be set. 2.5 V AVREF ADM1 = 0 ADM1 = 1 0.6 VDD 0.65 VDD VDD (2.7 to 6.0 V) 3. The time from conversion start instruction execution to conversion end (EOC=1) (40.1 s : at fX = 4.19 MHz) 4. The time from conversion start instruction execution to sampling end (10.5 s : at fX = 4.19 MHz) 49 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) AC Timing Test Points (excluding X1 and XT1 inputs): 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD Clock Timings: 1/fX tXL tXH X1 Input VDD -0.5 V 0.4 V 1/fXT tXTL tXTH XT1 Input VDD -0.5 V 0.4 V TI0 Timings: 1/fTI tTIL tTIH TI0 50 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Serial Transfer Timing 3-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI tKSO1 Input Data SO Output Data 2-wire serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0,1 tKSO2 51 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tSIK3,4 tKSB tSBL tSBH tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tSIK3,4 tKSB tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-3 RESET Input Timing tRSL RESET 52 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = -40 to +85 C) Parameter Data retention supply voltage Data retention supply current Release signal setting time Oscillation stabilization wait time Note2 Note 1 Symbol VDDDR IDDDR tSREL Conditions MIN. 2.0 TYP. MAX. 6.0 Unit V VDDDR = 2.0 V 0 Release by RESET 0.1 10 A s 217/fx Note3 ms ms tWAIT Release by interrupt request Notes 1. Current which flows in the on-chip pull-up resistor is not included. 2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 3. Depends on the basic interval timer mode register (BTM) settings (See the table below). Wait Time (Figures in parentheses are for operation at fx = 4.19 MHz) 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms) BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Data Retention Timing (STOP mode release by RESET) Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode VDD VDDDR STOP Instruction Execution tSREL RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT Mode STOP Mode Data Retention Mode Operating Mode VDD VDDDR STOP Instruction Execution tSREL Standby Release Signal (Interrupt Request) tWAIT 53 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 11. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) IDD vs VDD (Main system clock: 4.19-MHz crystal resonator) (Ta=25 C) X1 X2 Crystal resonator 4.19 MHz XT1 Crystal resonator 32.768 kHz XT2 330 k 5.0 3.0 PCC=0011 22 pF 22 pF 18 pF 18 pF PCC=0010 1.0 PCC=0000 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply Current IDD [mA] 0.1 0.05 Subsystem clock operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode 0.01 0.005 0.001 0 2 4 Supply Voltage VDD [V] 6 8 54 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) IDD vs VDD (Main system clock: 2.0-MHz crystal resonator) (Ta=25 C) X1 X2 Crystal resonator 2.0 MHz XT1 Crystal resonator 32.768 kHz XT2 330 k 5.0 3.0 22 pF 22 pF 18 pF 18 pF PCC=0011 1.0 PCC=0010 0.5 PCC=0000 Main system clock HALT mode + 32 kHz oscillation Supply Current IDD [mA] 0.1 0.05 Subsystem clock operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode 0.01 0.005 0.001 0 2 4 Supply Voltage VDD [V] 6 8 55 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) IDD vs VDD (Main system clock: 4.19-MHz ceramic resonator) (Ta=25 C) X1 X2 Ceramic resonator 4.19 MHz XT1 Crystal resonator 32.768 kHz XT2 330 k 5.0 3.0 PCC=0011 30 pF 30 pF 18 pF 18 pF PCC=0010 1.0 PCC=0000 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply Current IDD [mA] 0.1 0.05 Subsystem clock operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode 0.01 0.005 0.001 0 2 4 Supply Voltage VDD [V] 6 8 56 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) IDD vs VDD (Main system clock: 2.0-MHz ceramic resonator) (Ta=25 C) X1 X2 Ceramic resonator 2.0 MHz XT1 Crystal resonator 32.768 kHz XT2 330 k 5.0 3.0 30 pF 30 pF 18 pF 18 pF PCC=0011 PCC=0010 PCC=0000 0.5 Main system clock HALT mode + 32 kHz oscillation 1.0 Supply Current IDD [mA] 0.1 0.05 Subsystem clock operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode 0.01 0.005 0.001 0 2 4 Supply Voltage VDD [V] 6 8 57 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) IDD vs fX 2.0 X1 X2 IDD vs fX (VDD = 5 V, Ta=25 C) 0.5 X1 X2 (VDD = 3 V, Ta=25 C) PCC=0011 0.4 1.5 PCC=0010 0.3 PCC=0010 IDD [mA] PCC=0011 1.0 IDD [mA] 0.2 PCC=0000 0.5 PCC=0000 0.1 Main system clock HALT mode 0 0 1 2 3 fx [MHz] 4 Main system clock HALT mode 5 6 0 0 1 2 3 fx [MHz] 4 5 6 IOL vs VOL (Port 0) 40 (Ta=25 C) 30 IOL vs VOL (Ports 2, 6) (Ta=25 C) 25 VDD=5 V 30 VDD=6 V VDD=4 V VDD=5 V VDD=4 V VDD=3 V 20 VDD=6 V VDD=2.7 V VDD=3 V IOL [mA] 20 VDD=2.7 V IOL [mA] 15 10 10 5 0 0 1 2 VOL [V] 3 4 5 0 0 1 VOL [V] 2 3 58 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) IOL vs VOL (Port 3) 40 (Ta=25 C) IOL vs VOL (Ports 4, 5) 40 (Ta=25 C) 30 VDD=6 V VDD=5 V VDD=4 V VDD=3 V 30 VDD=5 V VDD=4 V VDD=6 V VDD=3 V VDD=2.7 V IOL [mA] IOL [mA] 20 20 VDD=2.7 V 10 10 0 0 1 2 VOL [V] 3 4 5 0 0 1 2 VOL [V] 3 4 5 IOH vs VOH 15 (Ta=25 C) 10 VDD=6 V VDD=5 V VDD=4 V VDD=3 V VDD=2.7 V IOH [mA] 5 0 0 1 2 VDD - VOH [V] 3 4 59 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 12. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 A 21 K L I G J H F C D N M B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A B C D F G H I J K L M N R 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15 INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1 5 Remark The outline dimensions and materials of ES versions are the same as for mass-produced versions. 60 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 44 PIN PLASTIC QFP ( 10) A B 33 34 23 22 detail of lead end C D S 44 1 12 11 F G H IM J K P N L P44GB-80-3B4-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 13.6 0.4 10.0 0.2 10.0 0.2 13.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.535+0.017 -0.016 0.394+0.008 -0.009 0.394+0.008 -0.009 0.535+0.017 -0.016 0.039 0.039 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX. M 55 Q Remark The outline dimensions and materials of ES versions are the same as for mass-produced versions. 5 61 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) 5 13. RECOMMENDED SOLDERING CONDITIONS Solder the PD75064, 75066, 75068 under the soldering conditions indicated below. For further information on the recommended soldering conditions, refer to information document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (IEI-1207)". For soldering methods and conditions other than those of recommended, consult NEC. Table 13-1. Soldering Conditions for Surface Mounting Devices PD75064GB-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) PD75066GB-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) PD75068GB-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) PD75064GB(A)-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) PD75066GB(A)-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) PD75068GB(A)-xxx-3B4 : 44-pin plastic QFP (10 x 10 mm) Soldering method Infrared ray reflow Soldering conditions max. (210 C min.), Number of reflow processes : 2 or less Symbol Peak temperature of package surface : 235 C, Time : 30 seconds IR35-00-2 VPS Peak temperature of package surface : 215 C, Time : 40 seconds VP15-00-2 max. (200 C min.), Number of reflow processes : 2 or less Wave soldering WS60-00-1 Partial heating -- Caution Do not apply two or more soldering methods (except partial heating method) to the same device. 62 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) Table 13-2. Soldering Conditions for Through-Hole Type Devices PD75064CU-xxx : 42-pin plastic shrink DIP (600 mil) PD75066CU-xxx : 42-pin plastic shrink DIP (600 mil) PD75068CU-xxx : 42-pin plastic shrink DIP (600 mil) PD75064CU(A)-xxx : 42-pin plastic shrink DIP (600 mil) PD75066CU(A)-xxx : 42-pin plastic shrink DIP (600 mil) PD75068CU(A)-xxx : 42-pin plastic shrink DIP (600 mil) Soldering method Wave soldering (Only leads) Partial heating Soldering conditions Soldering bath temperature : 260 C max., Time : 10 seconds max. Pin temperature : 300 C max., Time : 3 seconds max. (per pin) Caution Solder only the leads by means of wave soldering , and exercise care that the jetted solder does not come in contact with the package. 63 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A). Hardware IE-75000-R IE-75001-R IE-75000-R-EM EP-75068CU-R EP-75068GB-R EV-9200G-44 PG-1500 PA-75P008CU Software IE control program PG-1500 controller RA75X relocatable assembler Note2 Note1 In-circuit emulator for 75X series Emulation board for IE-75000-R or IE-75001-R Emulation probe for all shrink DIP versions of this series Emulation probe for all QFP versions of this series. A 44-pin conversion socket EV-9200G-44 is contained in this product. PROM programming equipment An adapter for connecting the PG-1500 to the PD75P068CU/GB. Host machines: PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A IBM PC/AT TM Note3 ) (refer to OS for IBM PC) Notes 1. Available for maintenance only 2. The IE-75000-R-EM is not installed in the IE-75001-R. 3. Ver. 5.00/5.00A has the task swap function, but it cannot be used with this software. 5 OS for IBM PC The following products are supported as OS for IBM PCs. OS PC DOSTM MS-DOS IBM DOSTM Version Ver. 5.02 to Ver. 6.1 Ver. 3.30 to Ver. 5.00 J5.02/V Note2 Note1 , 5.0/V Note2 Notes 1. Ver. 5.0 and later have the task swap function, but it cannot be used with this software. 2. Only the English mode is supported. Remark For development tools supplied by third-party manufacturers, refer to 75X Series Selection Guide (IF-1027). 64 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to device Document User's Manual Instruction Quick Reference Application Note 75X Series Selection Guide Doc. No. IEU-1366 -- IEA-1296 IF-1027 Documents related to development tool Document Hardware IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual EP-75068CU-R User's Manual EP-75068GB-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual Doc. No. EEU-1416 EEU-1294 EEU-1429 EEU-1428 EEU-1335 EEU-1346 EEU-1363 EEU-1291 Other related documents Document Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer-Related Product Guide - Third Party Products Doc. No. IEI-1231 IEI-1207 IEI-1209 -- -- MEI-1202 -- Caution The contents of the documents listed above are subject to change without prior notice to users. Make sure to use the latest edition when starting design. 65 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) [MEMO] 66 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 67 PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A) No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. |
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